VLSI Important Question Paper

EC 2354 – VLSI DESIGN

1. Explain with neat diagram the SOI process and mention Its advantages and Disadvantages.

2. Discuss the steps involved in IC fabrication Process.

3. Describe n-well process in detail.

4. (i) An NMOS transistor has the following parameters : gate oxide thickness = 10 nm, relative permittivity of gate oxide = 3.9,electron mobility = 520 cm2/V-sec, threshold voltage = 0.7 V, permittivity of free space = 8.85 × 10 -14F/cm and (W/L) = 8.Calculate the drain current when ( VGS = 2 V and VDS = 1.2 V) and( VGS = 2 V and VDS= 2 V) and also compute the gate oxide capacitance per unit area. Note that W and L refer to the width and length of the channel respectively. (8) (ii) Draw and explain the DC and transfer characteristics of a CMOS inverter with necessary conditions for the different regions of operation. (8)

5. Explain in detail about Channel length modulation , constant field scaling and constant voltage scaling.

6. Explain the working principle of n-MOS enhancement transistor with various modes of operation.

7. Derive the equation of threshold voltage in PMOS enhancement transistor.

8. With necessary equations , Explain in Detail about: (i) short Current effect (ii) Narrow channel effect.

9. Explain in detail about the operation of Conventional and dynamic CMOS , domino and NP domino logic with necessary diagram.

10. Explain the detail about pseudo n-MOS gate with neat circuit diagram.

11. (i) Draw the Circuit Diagram of the CMOS SR latch and explain in detail. (ii) Along with necessary input and output waveforms of the CMOS DFF negative triggered master slave D flip flop.

12. Explain in detail about : Pseudo random pattern generator and output response analyser.

13. Describe the Adhoc testing and scan based approaches to design for testability in detail.

14. Explain in detail about sequence of scan based technique.

15. Explain the following : (i) Silicon debug principles. (ii) Fault models

16. With the essential circuit modules , explain in detail the BIST technique.

17. Draw the three input CMOS NOR and NAND gate and write the Verilog switch level modelling.

18. Study all the Verilog coding you have done in VLSI DESIGN LAB(For All Types of modeling)

19. Write HDL Code for ripple Carry adder with Circuit diagram.

20.Explain In detail about gate-level modelling.